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| ASAHI KASEI [AK4647] AK4647 Stereo CODEC with MIC/HP-AMP GENERAL DESCRIPTION The AK4647 features a stereo CODEC with a built-in Microphone-Amplifier and Headphone-Amplifier. Built-in PLL circuit supports an easy interface with variable systems. The AK4647 is available in a 48pin LQFP, utilizing less board space than competitive offerings. FEATURES 1. Recording Function * Stereo Mic Input (Full-differential or Single-ended) * Stereo Line Input * MIC Amplifier (+32dB/+26dB/+20dB or 0dB) * Digital ALC (Automatic Level Control) (+36dB -54dB, 0.375dB Step, Mute) * ADC Performance: S/(N+D): 83dB, DR, S/N: 86dB (MIC-Amp=+20dB) S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB) * Wind-noise Reduction Filter * Stereo Separation Emphasis * Programmable EQ 2. Playback Function * Digital De-emphasis Filter (tc=50/15s, fs=32kHz, 44.1kHz, 48kHz) * Bass Boost * Soft Mute * Digital Volume (+12dB -115.0dB, 0.5dB Step, Mute) * Digital ALC (Automatic Level Control) (+36dB -54dB, 0.375dB Step, Mute) * Stereo Separation Emphasis * Stereo Line Output - Performance: S/(N+D): 88dB, S/N: 92dB * Stereo Headphone-Amp - S/(N+D): 70dB, S/N: 90dB - Output Power: 62mW@16 (HVDD=3.3V) - Pop Noise Free at Power ON/OFF * Analog Mixing: Mono Input 3. Power Management 4. Master Clock: (1) PLL Mode * Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin) 1fs (LRCK pin) 32fs or 64fs (BICK pin) (2) External Clock Mode * Frequencies: 256fs, 512fs or 1024fs (MCKI pin) 5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs MS0566-E-00 -1- 2006/11 ASAHI KASEI [AK4647] 6. Sampling Rate: * PLL Slave Mode (LRCK pin): 7.35kHz 48kHz * PLL Slave Mode (BICK pin): 7.35kHz 48kHz * PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz * PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz * EXT Slave Mode: 7.35kHz 48kHz (256fs), 7.35kHz 26kHz (512fs), 7.35kHz 13kHz (1024fs) 7. P I/F: 3-wire Serial, I2C Bus (Ver 1.0, 400kHz High Speed Mode) 8. Master/Slave mode 9. Audio Interface Format: MSB First, 2's complement * ADC : 16bit MSB justified, I2S * DAC : 16bit MSB justified, 16bit LSB justified, 16-24bit I2S 10. Ta = -40 85C 11. Power Supply: * AVDD, DVDD: 2.6 3.6V (typ. 3.3V) * HVDD: 2.6 5.25V (typ. 3.3V/5.0V) 12. Package: 48pin LQFP Block Diagram AVDD PMMP AVSS VCOM DVDD DVSS MPWR MIC Power Supply PMADL I2C Control Register CSN CCLK CDTI PMADL or PMADR LIN1 Internal MIC RIN1 MIC-Amp LIN2 PMADR A/D HPF Wind-Noise Reduction Stereo Separation PDN ALC External MIC RIN2 or BICK LRCK SDTO Audio I/F SDTI Line In PMLO LOUT Line Out ROUT PMHPL PMDAC HPL Headphone HPR MUTET PMHPR D/A Stereo DATT Bass ALC Separation SMUTE Boost HPF PMPLL MCKO PLL MCKI VCOC PMBP HVDD HVSS MIN Figure 1. Block Diagram MS0566-E-00 -2- 2006/11 ASAHI KASEI [AK4647] Ordering Guide AK4647VN AKD4647 -40 +85C 48pin LQFP (0.5mm pitch) Evaluation board for AK4647 Pin Layout MUTET TEST2 TEST1 MCKO HVDD HVSS MCKI 26 HPR HPL NC NC 36 33 32 30 28 35 34 31 29 27 25 NC NC NC ROUT LOUT NC MIN NC RIN2/IN2- LIN2/IN2+ LIN1/IN1- RIN1/IN1+ MPWR 37 38 39 40 41 42 43 44 45 46 47 48 10 11 1 2 5 3 6 7 8 4 9 12 24 23 22 21 NC DVSS DVDD BICK LRCK NC SDTO SDTI CDTI/SDA CCLK/SCL CSN/CAD0 NC AK4647VQ Top View 20 19 18 17 16 15 14 13 VCOM AVDD I2C NC NC NC AVSS MS0566-E-00 -3- VCOC PDN NC NC NC 2006/11 ASAHI KASEI [AK4647] PIN/FUNCTION No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name NC VCOM AVSS NC AVDD VCOC I2C NC PDN NC NC NC NC CSN CAD0 CCLK SCL CDTI SDA SDTI SDTO NC LRCK BICK DVDD DVSS NC I/O O O I I I I I I I I/O I O I/O I/O Function No Connect. No internal bonding. This pin should be left floating. Common Voltage Output Pin, 0.45 x AVDD Bias voltage of ADC inputs and DAC outputs. Analog Ground Pin No Connect. No internal bonding. This pin should be left floating. Analog Power Supply Pin Output Pin for Loop Filter of PLL Circuit This pin should be connected to AVSS with one resistor and capacitor in series. Control Mode Select Pin "H": I2C Bus, "L": 3-wire Serial No Connect. No internal bonding. This pin should be left floating. Power-Down Mode Pin "H": Power-up, "L": Power-down, reset and initializes the control register. No Connect. No internal bonding. This pin should be left floating. No Connect. No internal bonding. This pin should be left floating. No Connect. No internal bonding. This pin should be left floating. No Connect. No internal bonding. This pin should be left floating. Chip Select Pin (I2C pin = "L": 3-wire Serial Mode) Chip Address 0 Select Pin (I2C pin = "H": I2C Bus Mode) Control Data Clock Pin (I2C pin = "L": 3-wire Serial Mode) Control Data Clock Pin (I2C pin = "H": I2C Bus Mode) Control Data Input Pin (I2C pin = "L": 3-wire Serial Mode) Control Data Input Pin (I2C pin = "H": I2C Bus Mode) Audio Serial Data Input Pin Audio Serial Data Output Pin No Connect. No internal bonding. This pin should be left floating. Input / Output Channel Clock Pin Audio Serial Data Clock Pin Digital Power Supply Pin Digital Ground Pin No Connect. No internal bonding. This pin should be left floating. MS0566-E-00 -4- 2006/11 ASAHI KASEI [AK4647] No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name NC MCKI MCKO NC NC TEST1 TEST2 HVDD HVSS HPR HPL MUTET NC NC ROUT LOUT NC MIN NC RIN2 IN2- LIN2 IN2+ LIN1 IN1- RIN1 IN1+ MPWR I/O I O O O O O O I I I I I I I I I O Function No Connect. No internal bonding. This pin should be left floating. External Master Clock Input Pin Master Clock Output Pin No Connect. No internal bonding. This pin should be left floating. No Connect. No internal bonding. This pin should be left floating. Test Pin 1 This pin should be open. Test Pin 2 This pin should be open. Headphone & Speaker Amp Power Supply Pin Headphone & Speaker Amp Ground Pin Rch Headphone-Amp Output Pin Lch Headphone-Amp Output Pin Mute Time Constant Control Pin Connected to HVSS pin with a capacitor for mute time constant. No Connect. No internal bonding. This pin should be left floating. No Connect. No internal bonding. This pin should be left floating. Rch Stereo Line Output Pin Lch Stereo Line Output Pin No Connect. No internal bonding. This pin should be left floating. Mono Signal Input Pin No Connect. No internal bonding. This pin should be left floating. Rch Analog Input 2 Pin (MDIF2 bit = "0": Single-ended Input) Microphone Negative Input 2 Pin (MDIF2 bit = "1": Full-differential Input) Lch Analog Input 2 Pin (MDIF2 bit = "0": Single-ended Input) Microphone Positive Input 2 Pin (MDIF2 bit = "1": Full-differential Input) Lch Analog Input 1 Pin (MDIF1 bit = "0": Single-ended Input) Microphone Negative Input 1 Pin (MDIF1 bit = "1": Full-differential Input) Rch Analog Input 1 Pin (MDIF1 bit = "0": Single-ended Input) Microphone Positive Input 1 Pin (MDIF1 bit = "1": Full-differential Input) MIC Power Supply Pin Note 1. All input pins except analog input pins (MIN, LIN1, RIN1, LIN2, RIN2) should not be left floating. Note 2. AVDD or AVSS voltage should be input to I2C pin. MS0566-E-00 -5- 2006/11 ASAHI KASEI [AK4647] Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name MPWR, VCOC, HPR, HPL, MUTET, ROUT, LOUT, Analog MIN, RIN2/IN2-, LIN2/IN2+, LIN1/IN1-, RIN1/IN1+ MCKO Digital MCKI Setting These pins should be open. This pin should be open. This pin should be connected to DVSS. ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS, HVSS=0V; Note 3) Parameter Symbol min Power Supplies: Analog AVDD -0.3 Digital DVDD -0.3 Headphone-Amp HVDD -0.3 |AVSS - DVSS| (Note 4) GND1 |AVSS - HVSS| (Note 4) GND2 Input Current, Any Pin Except Supplies IIN Analog Input Voltage (Note 5) VINA -0.3 Digital Input Voltage (Note 6) VIND -0.3 Ambient Temperature (powered applied) Ta -40 Storage Temperature Tstg -65 max 6.0 6.0 6.0 0.3 0.3 10 AVDD+0.3 DVDD+0.3 85 150 Units V V V V V mA V V C C Note 3. All voltages with respect to ground. Note 4. AVSS, DVSS and HVSS must be connected to the same analog ground plane. Note 5. I2C, RIN2/IN2-, LIN2/IN2+, LIN1/IN1-, RIN1/IN1+ pins Note 6. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins Pull-up resistors at SDA and SCL pins should be connected to (DVDD+0.3)V or less voltage. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS, HVSS=0V; Note 3) Parameter Symbol min typ Power Supplies Analog AVDD 2.6 3.3 (Note 7) Digital DVDD 2.6 3.3 HP-Amp HVDD 2.6 3.3 / 5.0 Difference 0 AVDD-DVDD -0.3 Max 3.6 3.6 5.25 +0.3 Units V V V V Note 3. All voltages with respect to ground. Note 7. The power-up sequence between AVDD, DVDD and HVDD is not critical. When the power supplies are partially powered OFF, the AK4647 must be reset by bringing PDN pin "L" after these power supplies are powered ON again. When AVDD or HVDD is powered OFF, the power supply current of DVDD at power-down mode may be increased. DVDD should not be powered OFF while AVDD or HVDD is powered ON. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0566-E-00 -6- 2006/11 ASAHI KASEI [AK4647] ANALOG CHARACTERISTICS (Ta=25C; AVDD, DVDD, HVDD=3.3V; AVSS=DVSS=HVSS=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz 20kHz; unless otherwise specified) min typ max Parameter MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins; MDIF1 = MDIF2 bits = "0" (Single-ended inputs) Input MGAIN1-0 bits = "00" 40 60 80 Resistance MGAIN1-0 bits = "01", "10"or "11" 20 30 40 MGAIN1-0 bits = "00" 0 MGAIN1-0 bits = "01" +20 Gain MGAIN1-0 bits = "10" +26 MGAIN1-0 bits = "11" +32 MIC Amplifier: IN1+, IN1-, IN2+, IN2- pins; MDIF1 = MDIF2 bits = "1" (Full-differential input) Maximum Input Voltage (Note 8) MGAIN1-0 bits = "01" 0.228 MGAIN1-0 bits = "10" 0.114 MGAIN1-0 bits = "11" 0.057 MIC Power Supply: MPWR pin Output Voltage (Note 9) 2.22 2.47 2.72 Load Resistance 0.5 Load Capacitance 30 ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2 pins ADC IVOL, IVOL=0dB, ALC=OFF Resolution 16 (Note 11) 0.168 0.198 0.228 Input Voltage (Note 10) (Note 12) 1.68 1.98 2.28 (Note 11) 71 83 S/(N+D) (-1dBFS) (Note 12) 88 (Note 11) 76 86 D-Range (-60dBFS, A-weighted) (Note 12) 95 (Note 11) 76 86 S/N (A-weighted) (Note 12) 95 (Note 11) 75 90 Interchannel Isolation (Note 12) 100 (Note 11) 0.1 0.8 Interchannel Gain Mismatch (Note 12) 0.1 0.8 Units k k dB dB dB dB Vpp Vpp Vpp V k pF Bits Vpp Vpp dBFS dBFS dB dB dB dB dB dB dB dB Note 8. The voltage difference between IN1/2+ and IN1/2- pins. AC coupling capacitor should be inserted in series at each input pin. Full-differential mic input is not available at MGAIN1-0 bits = "00". Maximum input voltage of IN1+, IN1-, IN2+ and IN2- pins is proportional to AVDD voltage, respectively. Vin = 0.069 x AVDD (max)@MGAIN1-0 bits = "01", 0.035 x AVDD (max)@MGAIN1-0 bits = "10", 0.017 x AVDD (max)@MGAIN1-0 bits = "11". When the signal larger than above value is input to IN1+, IN1-, IN2+ or IN2- pin, ADC does not operate normally. Note 9. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ) Note 10. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ)@MGAIN1-0 bits = "01" (+20dB), Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = "00" (0dB) Note 11. MGAIN1-0 bits = "01" (+20dB) Note 12. MGAIN1-0 bits = "00" (0dB) MS0566-E-00 -7- 2006/11 ASAHI KASEI [AK4647] min typ max Units Parameter DAC Characteristics: Resolution 16 Bits Stereo Line Output Characteristics: DAC LOUT, ROUT pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = "0", RL=10k Output Voltage (Note 13) LOVL bit = "0" 1.78 1.98 2.18 Vpp LOVL bit = "1" 2.25 2.50 2.75 Vpp S/(N+D) (-3dBFS) 78 88 dBFS S/N (A-weighted) 82 92 dB Interchannel Isolation 80 100 dB Interchannel Gain Mismatch 0.1 0.5 dB Load Resistance 10 k Load Capacitance 30 pF Headphone-Amp Characteristics: DAC HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB (Note 15) 1.58 1.98 2.38 Vpp Output Voltage (Note 14) (Note 16) 2.40 3.00 3.60 Vpp (Note 15) 60 70 dBFS S/(N+D) (-3dBFS) (Note 16) 80 dBFS (Note 15) 80 90 dB S/N (A-weighted) (Note 16) 90 dB (Note 15) 65 75 dB Interchannel Isolation (Note 16) 80 dB (Note 15) 0.1 0.8 dB Interchannel Gain Mismatch (Note 16) 0.1 0.8 dB (Note 15) 20 Load Resistance (Note 16) 100 C1 in Figure 2 30 pF Load Capacitance C2 in Figure 2 300 pF Note 13. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)@LOVL bit = "0". Note 14. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD(typ)@HPG bit = "0", 0.91 x AVDD(typ)@HPG bit = "1". Note 15. HPG bit = "0", HVDD=3.3V, RL=22.8. Note 16. HPG bit = "1", HVDD=5V, RL=100. HP-Amp HPL/HPR pin 47F 6.8 C1 C2 16 Figure 2. Headphone-Amp output circuit MS0566-E-00 -8- 2006/11 ASAHI KASEI [AK4647] min Parameter Mono Input: MIN pin (External Input Resistance=20k) Maximum Input Voltage (Note 17) Gain Note 18(Note 18) MIN LOUT/ROUT LOVL bit = "0" -4.5 LOVL bit = "1" MIN HPL/HPR HPG bit = "0" -24.5 HPG bit = "1" Power Supplies: Power Up (PDN pin = "H") All Circuit Power-up: AVDD+DVDD (Note 19) HVDD: HP-Amp Normal Operation No Output (Note 20) Power Down (PDN pin = "L") (Note 21) AVDD+DVDD+HVDD - typ 1.98 0 +2 -20 -16.4 max +4.5 -15.5 - Units Vpp dB dB dB dB 15 5 10 23 8 100 mA mA A Note 17. Maximum voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD x Rin / 20k (typ). Note 18. The gain is in inverse proportion to external input resistance. Note 19. PLL Master Mode (MCKI=12.288MHz) and PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMSPK = PMVCM = PMPLL = MCKO = PMBP = PMMP = M/S bits = "1". MPWR pin outputs 0mA. AVDD=11mA(typ), DVDD=4mA(typ). EXT Slave Mode (PMPLL = M/S = MCKO bits = "0"): AVDD=10mA(typ), DVDD=3mA(typ). Note 20. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMBP bits = "1" and PMSPK bit = "0". Note 21. All digital input pins are fixed to DVDD or DVSS. MS0566-E-00 -9- 2006/11 ASAHI KASEI [AK4647] FILTER CHARACTERISTICS (Ta=25C; AVDD, DVDD=2.6 3.6V; HVDD=2.6 5.25V; fs=44.1kHz; DEM=OFF; FIL1=FIL3=EQ=OFF) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 22) PB 0 17.3 kHz 0.16dB 19.4 kHz -0.66dB 19.9 kHz -1.1dB 22.1 kHz -6.9dB Stopband SB 26.1 kHz Passband Ripple PR dB 0.1 Stopband Attenuation SA 73 dB Group Delay (Note 23) GD 19 1/fs Group Delay Distortion 0 GD s ADC Digital Filter (HPF): (Note 24) Frequency Response (Note 22) -3.0dB FR 0.9 Hz 2.7 Hz -0.5dB 6.0 Hz -0.1dB DAC Digital Filter (LPF): Passband (Note 22) PB 0 19.6 kHz 0.1dB 20.0 kHz -0.7dB 22.05 kHz -6.0dB Stopband SB 25.2 kHz Passband Ripple PR dB 0.01 Stopband Attenuation SA 59 dB Group Delay (Note 23) GD 22 1/fs DAC Digital Filter (LPF) + SCF: FR dB Frequency Response: 0 20.0kHz 1.0 DAC Digital Filter (HPF): (Note 24) Frequency Response (Note 22) -3.0dB FR 0.9 Hz 2.7 Hz -0.5dB 6.0 Hz -0.1dB BOOST Filter: (Note 25) Frequency Response MIN FR 20Hz dB 5.76 100Hz dB 2.92 1kHz dB 0.02 MID FR 20Hz dB 10.80 100Hz dB 6.84 1kHz dB 0.13 MAX 20Hz FR dB 16.06 100Hz dB 10.54 1kHz dB 0.37 Note 22. The passband and stopband frequencies scale with fs (system sampling rate). For example, ADC is PB=0.454*fs (@-1.0dB). Each response refers to that of 1kHz. Note 23. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. Group delay of DAC part is 22/fs(typ) at PMADL=PMADR bits = "0". Note 24. When PMADL bit = "1" or PMADR bit = "1", the HPF of ADC is enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = "0", PMDAC bit = "1", the HPF of DAC is enabled but the HPF of ADC is disabled. Note 25. These frequency responses scale with fs. If a high-level and low frequency signal is input, the analog output clips to the full-scale. MS0566-E-00 - 10 - 2006/11 ASAHI KASEI [AK4647] DC CHARACTERISTICS (Ta=25C; AVDD, DVDD=2.6 3.6V; HVDD=2.6 5.25V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL High-Level Output Voltage VOH (Iout=-200A) DVDD-0.2 Low-Level Output Voltage VOL (Except SDA pin: Iout=200A) (SDA pin: Iout=3mA) VOL Input Leakage Current Iin - typ - Max 30%DVDD 0.2 0.4 10 Units V V V V V A SWITCHING CHARACTERISTICS (Ta=25C; AVDD, DVDD=2.6 3.6V; HVDD=2.6 5.25V; CL=20pF; unless otherwise specified) Parameter Symbol min typ max PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 27 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK MCKO Output Timing Frequency fMCK 0.2352 12.288 Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 256fs at fs=32kHz, 29.4kHz dMCK 33 LRCK Output Timing Frequency fs 7.35 48 Duty Cycle Duty 50 BICK Output Timing Period BCKO bit = "0" tBCK 1/(32fs) BCKO bit = "1" tBCK 1/(64fs) Duty Cycle dBCK 50 PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 27 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK MCKO Output Timing Frequency fMCK 0.2352 12.288 Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 256fs at fs=32kHz, 29.4kHz dMCK 33 LRCK Input Timing Frequency fs 7.35 48 Duty Duty 45 55 BICK Input Timing Period tBCK 1/(64fs) 1/(32fs) Pulse Width Low tBCKL 0.4 x tBCK Pulse Width High tBCKH 0.4 x tBCK - Units MHz ns ns MHz % % kHz % ns ns % MHz ns ns MHz % % kHz % ns ns ns MS0566-E-00 - 11 - 2006/11 ASAHI KASEI [AK4647] Parameter Symbol min PLL Slave Mode (PLL Reference Clock = LRCK pin) LRCK Input Timing Frequency fs 7.35 Duty Duty 45 BICK Input Timing Period tBCK 1/(64fs) Pulse Width Low tBCKL 130 Pulse Width High tBCKH 130 PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency fs 7.35 Duty Duty 45 BICK Input Timing Period PLL3-0 bits = "0010" tBCK PLL3-0 bits = "0011" tBCK Pulse Width Low tBCKL 0.4 x tBCK Pulse Width High tBCKH 0.4 x tBCK External Slave Mode MCKI Input Timing Frequency 256fs fCLK 1.8816 512fs fCLK 3.7632 1024fs fCLK 7.5264 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK Input Timing Frequency 256fs fs 7.35 512fs fs 7.35 1024fs fs 7.35 Duty Duty 45 BICK Input Timing Period tBCK 312.5 Pulse Width Low tBCKL 130 Pulse Width High tBCKH 130 Audio Interface Timing Master Mode tMBLR BICK "" to LRCK Edge (Note 26) -40 LRCK Edge to SDTO (MSB) tLRD -70 (Except I2S mode) tBSD BICK "" to SDTO -70 SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Slave Mode tLRB 50 LRCK Edge to BICK "" (Note 26) tBLR 50 BICK "" to LRCK Edge (Note 26) LRCK Edge to SDTO (MSB) tLRD (Except I2S mode) tBSD BICK "" to SDTO SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Note 26. BICK rising edge must not occur at the same time as LRCK edge. typ max Units - 48 55 1/(32fs) - kHz % ns ns ns 1/(32fs) 1/(64fs) - 48 55 - kHz % ns ns ns ns - 12.288 13.312 13.312 48 26 13 55 - MHz MHz MHz ns ns kHz kHz kHz % ns ns ns - 40 70 70 80 80 - ns ns ns ns ns ns ns ns ns ns ns MS0566-E-00 - 12 - 2006/11 ASAHI KASEI [AK4647] Parameter Control Interface Timing (3-wire Serial mode) CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 28) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Capacitive Load on Bus Pulse Width of Spike Noise Suppressed by Input Filter Power-down & Reset Timing PDN Pulse Width (Note 29) PMADL or PMADR "" to SDTO valid (Note 30) Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO Cb tSP tPD tPDV min 200 80 80 40 40 150 50 50 1.3 0.6 1.3 0.6 0.6 0 0.1 0.6 0 150 - typ 1059 max 400 0.3 0.3 400 50 - Units ns ns ns ns ns ns ns ns kHz s s s s s s s s s s pF ns ns 1/fs Note 27. . I2C is a registered trademark of Philips Semiconductors. Note 28. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 29. The AK4647 can be reset by the PDN pin = "L". Note 30. This is the count of LRCK "" from the PMADL or PMADR bit = "1". MS0566-E-00 - 13 - 2006/11 ASAHI KASEI [AK4647] Timing Diagram 1/fCLK VIH MCKI VIL tCLKH 1/fs tCLKL LRCK tLRCKH tLRCKL 1/fMCK 50%DVDD Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 MCKO tMCKL 50%DVDD dMCK = tMCKL x fMCK x 100 Figure 3. Clock Timing (PLL Master mode) LRCK 50%DVDD tBLR tBCKL 50%DVDD tLRD BICK tBSD SDTO tSDS tSDH 50%DVDD VIH SDTI VIL Figure 4. Audio Interface Timing (PLL Master mode) MS0566-E-00 - 14 - 2006/11 ASAHI KASEI [AK4647] 1/fCLK VIH MCKI VIL tCLKH 1/fs VIH LRCK VIL tLRCKH tBCK tLRCKL Duty = tLRCKH x fs x 100 = tLRCKL x fs x 100 VIH BICK VIL tBCKH fMCK tBCKL tCLKL MCKO tMCKL 50%DVDD dMCK = tMCKL x fMCK x 100 Figure 5. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin) 1/fCLK VIH MCKI VIL tCLKH 1/fs VIH LRCK VIL tLRCKH tBCK VIH BICK VIL tBCKH tBCKL tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tCLKL Figure 6. Clock Timing (EXT Slave mode) MS0566-E-00 - 15 - 2006/11 ASAHI KASEI [AK4647] VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRD tBSD SDTO tSDS MSB tSDH 50%DVDD VIH SDTI VIL Figure 7. Audio Interface Timing (PLL/EXT Slave mode) VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 C0 tCCK tCDH VIH R/W VIL Figure 8. WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI D2 D1 D0 VIL Figure 9. WRITE Data Input Timing MS0566-E-00 - 16 - 2006/11 ASAHI KASEI [AK4647] SDA tBUF tLOW tR tHIGH tF tSP VIH VIL VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop Figure 10. I2C Bus Mode PMADL bit or PMADR bit tPDV SDTO 50%DVDD Timing Figure 11. Power Down & Reset Timing 1 tPD PDN VIL Figure 12. Power Down & Reset Timing 2 MS0566-E-00 - 17 - 2006/11 ASAHI KASEI [AK4647] OPERATION OVERVIEW System Clock There are the following four clock modes to interface with external devices (see Table 1 and Table 2). Mode PMPLL bit M/S bit PLL3-0 bits PLL Master Mode 1 1 See Table 4 PLL Slave Mode 1 1 0 See Table 4 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 1 0 See Table 4 (PLL Reference Clock: LRCK or BICK pin) EXT Slave Mode 0 0 x Don't Care (Note 31) 0 1 x Note 31. If this mode is selected, the invalid clocks are output from MCKO pin when MCKO bit is "1". Table 1. Clock Mode Setting (x: Don't care) Mode PLL Master Mode PLL Slave Mode (PLL Reference Clock: MCKI pin) PLL Slave Mode (PLL Reference Clock: LRCK or BICK pin) EXT Slave Mode MCKO bit 0 1 0 1 0 0 MCKO pin "L" Selected by PS1-0 bits "L" Selected by PS1-0 bits "L" "L" MCKI pin Selected by PLL3-0 bits Selected by PLL3-0 bits GND BICK pin Output (Selected by BCKO bit) Input (Selectet by BCKO bit) Input (Selected by BCKO bit) Input ( 32fs) Figure Figure 13 Figure 14 Figure 15 Figure 17 - LRCK pin Output (1fs) Input (1fs) Input (1fs) Input (1fs) Selected by FS3-0 bits Table 2. Clock pins state in Clock Mode Master Mode/Slave Mode The M/S bit selects either master or slave mode. M/S bit = "1" selects master mode and "0" selects slave mode. When the AK4647 is power-down mode (PDN pin = "L") and exits reset state, the AK4647 is slave mode. After exiting reset state, the AK4647 goes to master mode by changing M/S bit = "1". When the AK4647 is used by master mode, LRCK and BICK pins are a floating state until M/S bit becomes "1". LRCK and BICK pins of the AK4647 should be pulled-down or pulled-up by the resistor (about 100k) externally to avoid the floating state. M/S bit Mode 0 Slave Mode 1 Master Mode Table 3. Select Master/Salve Mode Default MS0566-E-00 - 18 - 2006/11 ASAHI KASEI [AK4647] PLL Mode When PMPLL bit is "1", a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4647 is supplied to a stable clocks after PLL is powered-up (PMPLL bit = "0" "1") or sampling frequency changes. 1) Setting of PLL Mode Mode PLL3 bit 0 0 0 0 0 0 0 1 1 PLL2 bit 0 0 0 1 1 1 1 1 1 Others PLL1 bit 0 1 1 0 0 1 1 0 0 PLL0 bit 0 0 1 0 1 0 1 0 1 0 2 3 4 5 6 7 12 13 Others PLL Reference Clock Input Pin LRCK pin BICK pin BICK pin Input Frequency 1fs 32fs 64fs R and C of VCOC pin R[] C[F] 6.8k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 220n 4.7n 10n 4.7n 10n 4.7n 4.7n 4.7n 4.7n 10n 10n PLL Lock Time (max) 160ms 2ms 4ms 2ms 4ms 40ms 40ms 40ms 40ms 40ms 40ms Default MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 13.5MHz MCKI pin 27MHz N/A Table 4. Setting of PLL Mode (*fs: Sampling Frequency) 2) Setting of sampling frequency in PLL Mode When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5. Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency 0 0 0 0 0 8kHz Default 1 0 0 0 1 12kHz 2 0 0 1 0 16kHz 3 0 0 1 1 24kHz 4 0 1 0 0 7.35kHz 5 0 1 0 1 11.025kHz 6 0 1 1 0 14.7kHz 7 0 1 1 1 22.05kHz 10 1 0 1 0 32kHz 11 1 0 1 1 48kHz 14 1 1 1 0 29.4kHz 15 1 1 1 1 44.1kHz Others Others N/A Table 5. Setting of Sampling Frequency at PMPLL bit = "1" (Reference Clock = MCKI pin) When PLL reference clock input is LRCK or BICK pin the sampling frequency is selected by FS3 and FS1-0 bits. (See Table 6). FS2 bit is "don't care". Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range 0 Don't care 0 Default 0 0 7.35kHz fs 8kHz 0 Don't care 1 1 0 8kHz < fs 12kHz 0 Don't care 0 2 1 12kHz < fs 16kHz 0 Don't care 1 3 1 16kHz < fs 24kHz 1 Don't care 0 6 1 24kHz < fs 32kHz 1 Don't care 1 7 1 32kHz < fs 48kHz Others Others N/A Table 6. Setting of Sampling Frequency at PMPLL bit = "1" (Reference Clock = LRCK or BICK pin) MS0566-E-00 - 19 - 2006/11 ASAHI KASEI [AK4647] PLL Unlock State 1) PLL Master Mode (PMPLL bit = "1", M/S bit = "1") In this mode, LRCK and BICK pins go to "L" and irregular frequency clock is output from MCKO pins at MCKO bit is "1" before the PLL goes to lock state after PMPLL bit = "0" "1". If MCKO bit is "0", MCKO pin goes to "L" (see Table 7). After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state after a period of 1/fs. When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to "L" by setting PMPLL bit to "0". MCKO pin BICK pin MCKO bit = "0" MCKO bit = "1" After that PMPLL bit "0" "1" "L" Output Invalid "L" Output PLL Unlock (except above case) "L" Output Invalid Invalid PLL Lock "L" Output See Table 9 See Table 10 Table 7. Clock Operation at PLL Master Mode (PMPLL bit = "1", M/S bit = "1") PLL State 2) PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = "0" "1". After that, the clock selected by Table 9 is output from MCKO pin when PLL is locked. ADC and DAC output invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing "0" to DACL, DACH and DACS bits. MCKO pin MCKO bit = "0" MCKO bit = "1" After that PMPLL bit "0" "1" "L" Output Invalid PLL Unlock "L" Output Invalid PLL Lock "L" Output Output Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = "0", M/S bit = "0") PLL State LRCK pin "L" Output Invalid 1fs Output MS0566-E-00 - 20 - 2006/11 ASAHI KASEI [AK4647] PLL Master Mode (PMPLL bit = "1", M/S bit = "1") When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits (see Table 9) and the output is enabled by MCKO bit. The BICK output frequency is selected among 32fs or 64fs, by BCKO bit (see Table 10). 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz AK4647 MCKI MCKO BICK LRCK SDTO SDTI 256fs/128fs/64fs/32fs 32fs, 64fs 1fs DSP or P MCLK BCLK LRCK SDTI SDTO Figure 13. PLL Master Mode Mode PS1 bit PS0 bit MCKO pin 0 0 0 256fs Default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = "1") BICK Output Frequency 0 32fs Default 1 64fs Table 10. BICK Output Frequency at Master Mode BCKO bit MS0566-E-00 - 21 - 2006/11 ASAHI KASEI [AK4647] PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the AK4647 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 4). a) PLL reference clock: MCKI pin BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not matter. MCKO pin outputs the frequency selected by PS1-0 bits (see Table 9) and the output is enabled by MCKO bit. Sampling frequency can be selected by FS3-0 bits (see Table 5). 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz, AK4647 MCKI MCKO BICK LRCK SDTO SDTI 256fs/128fs/64fs/32fs 32fs 1fs DSP or P MCLK BCLK LRCK SDTI SDTO Figure 14. PLL Slave Mode 1 (PLL Reference Clock: LRCK or BICK pin) MS0566-E-00 - 22 - 2006/11 ASAHI KASEI [AK4647] b) PLL reference clock: BICK or LRCK pin Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (see Table 6). AK4647 MCKO MCKI BICK LRCK SDTO SDTI 32fs or 64fs 1fs BCLK LRCK SDTI SDTO DSP or P Figure 15. PLL Slave Mode 2 (PLL Reference Clock: BICK pin) AK4647 MCKO MCKI BICK LRCK SDTO SDTI 32fs 1fs BCLK LRCK SDTI SDTO DSP or P Figure 16. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin) The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = "1", PMADR bit = "1" or PMDAC bit = "1"). If these clocks are not provided, the AK4647 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = "0"). MS0566-E-00 - 23 - 2006/11 ASAHI KASEI [AK4647] EXT Slave Mode (PMPLL bit = "0", M/S bit = "0") When PMPLL bit is "0", the AK4647 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK (32fs). The master clock (MCKI) should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (see Table 11). Mode 0 1 2 3 Others MCKI Input Sampling Frequency Frequency Range Don't care 0 0 256fs 7.35kHz 48kHz Don't care 0 1 1024fs 7.35kHz 13kHz Don't care 1 0 256fs 7.35kHz 48kHz Don't care 1 1 512fs 7.35kHz 26kHz Others N/A N/A Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = "0", M/S bit = "0") FS3-2 bits FS1 bit FS0 bit Default The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output through LOUT/ROUT pins at fs=8kHz is shown in Table 12. S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 83dB 512fs 93dB 1024fs 93dB Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins MCKI The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = "1", PMADR bit = "1" or PMDAC bit = "1"). If these clocks are not provided, the AK4647 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = "0"). AK4647 MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK SDTO SDTI 32fs 1fs MCLK BCLK LRCK SDTI SDTO DSP or P Figure 17. EXT Slave Mode MS0566-E-00 - 24 - 2006/11 ASAHI KASEI [AK4647] System Reset Upon power-up, the AK4647 should be reset by bringing the PDN pin = "L". This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from "0" to "1" at PMDAC bits is "0". The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the ADC digital data outputs of both channels are forced to a 2's compliment, "0". The ADC output reflects the analog input signal after the initialization cycle is complete. When PMDAC bit is "1", the ADC does not require an initialization cycle. The DAC enters an initialization cycle that starts when the PMDAC bit is changed from "0" to "1" at PMADL and PMADR bits are "0". The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, "0". The DAC output reflects the digital input data after the initialization cycle is complete. When PMADC or PMADR bit is "1", the DAC does not require an initialization cycle. Audio Interface Format Three types of data formats are available and are selected by setting the DIF1-0 bits (seeTable 13). In all modes, the serial data is MSB first, 2's complement format. Audio interface formats can be used in both master and slave modes. LRCK and BICK are output from the AK4647 in master mode, but must be input to the AK4647 in slave mode. The SDTO is clocked out on the falling edge ("") of BICK and the SDTI is latched on the rising edge (""). Mode 0 1 2 3 DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 SDTO (ADC) SDTI (DAC) N/A N/A MSB justified LSB justified MSB justified MSB justified I2S compatible I2S compatible Table 13. Audio Interface Format BICK N/A 32fs 32fs 32fs Figure Figure 18 Figure 19 Figure 20 Default If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, "-1" at 16bit data is converted to "-1" at 8-bit data. And when the DAC playbacks this 8-bit data, "-1" at 8-bit data will be converted to "-256" at 16-bit data and this is a large offset. This offset can be removed by adding the offset of "128" to 16-bit data before converting to 8-bit data. LRCK 0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i) 15 14 13 Don't Care 15:MSB, 0:LSB Lch Data Rch Data 10 15 14 10 15 14 13 Don't Care 10 15 14 210 15 15 14 13 15 14 13 0123 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 14 13 15 16 17 18 31 0 1 2 3 7 6 5 4 3 2 1 0 15 7 6 5 4 3 2 1 0 15 15 16 17 18 31 0 1 Figure 18. Mode 1 Timing MS0566-E-00 - 25 - 2006/11 ASAHI KASEI [AK4647] LRCK 0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i) 15 14 13 15 14 13 15:MSB, 0:LSB Lch Data Rch Data 10 10 Don't Care 15 14 13 15 14 13 10 10 Don't Care 15 15 15 14 13 15 14 13 0123 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 14 13 15 16 17 18 31 0 1 2 3 7 6 5 4 3 2 1 0 15 7 6 5 4 3 2 1 0 15 15 16 17 18 31 0 1 Figure 19. Mode 2 Timing LRCK 0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i) 15 14 15 14 210 210 Don't Care 15 14 15 14 210 210 Don't Care 0 15 14 0 15 14 0123 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 15 14 15 16 17 18 31 0 1 2 3 876543210 876543210 15 16 17 18 31 0 1 15:MSB, 0:LSB Lch Data Rch Data Figure 20. Mode 3 Timing Mono/Stereo Mode PMADL and PMADR bits set mono/stereo ADC operation. PMADL bit 0 0 1 1 PMADR bit ADC Lch data 0 All "0" 1 Rch Input Signal 0 Lch Input Signal 1 Lch Input Signal Table 14. Mono/Stereo ADC operation ADC Rch data All "0" Rch Input Signal Lch Input Signal Rch Input Signal Default MS0566-E-00 - 26 - 2006/11 ASAHI KASEI [AK4647] Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.9Hz (@fs=44.1kHz) and scales with sampling rate (fs). When PMADL bit = "1" or PMADR bit = "1", the HPF of ADC is enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = "0", PMDAC bit = "1", the HPF of DAC is enabled but the HPF of ADC is disabled. MIC/LINE Input Selector The AK4647 has input selector. When MDIF1 and MDIF2 bits are "0", INL and INR bits select LIN1/LIN2 and RIN1/RIN2, respectively. When MDIF1 and MDIF2 bits are "1", LIN1, RIN1, LIN2 and RIN2 pins become IN1-, IN1+, IN2+ and IN2- pins respectively. In this case, full-differential input is available (Figure 22). When full-differential input is used, the signal should not be input to the pins marked by "X" in. MDIF1 bit 0 0 0 0 0 1 1 Others MDIF2 bit 0 0 0 0 1 0 1 INL bit 0 0 1 0 0 0 0 Lch LIN1 LIN1 LIN2 LIN2 LIN1 IN1+/- IN1+/- N/A Table 15. MIC/Line In Path Select INR bit 0 1 0 1 0 1 0 Rch RIN1 RIN2 RIN1 RIN2 IN2+/- RIN2 IN2+/- N/A Default Pin RIN2 LIN1 RIN1 LIN2 MDIF1 bit MDIF2 bit IN1+ IN2+ IN2- IN1- 0 0 O O O O 0 1 O X O O 1 0 O O X O 1 1 O O O O Table 16. Handling of MIC/Line Input Pins ("-": N/A; "X": Signal should not be input.) Register MS0566-E-00 - 27 - 2006/11 ASAHI KASEI [AK4647] AK4647 INL bit LIN1/IN1- pin ADC Lch RIN1/IN1+ pin MDIF1 bit INR bit RIN2/IN2- pin LIN2/IN2+ pin MDIF2 bit ADC Rch Figure 21. Mic/Line Input Selector AK4647 MPWR pin 1k IN1- pin IN1+ pin 1k MIC-Amp A/D SDTO pin Figure 22. Connection Example for Full-differential Mic Input (MDIF1/2 bits = "1") In case that IN1+/- pins are used as full-differential mic input and LIN2/RIN2 pins are used as stereo line input, it is recommended that the following two modes are set by register setting according to each case. MDIF1 bit 1 0 MDIF2 bit 0 0 INL1 bit INL0 bit INR1 bit INR0 bit 0 0 0 1 0 1 0 1 Table 17. MIC/Line In Path Select Example Lch IN1+/- LIN2 Rch RIN2 RIN2 MS0566-E-00 - 28 - 2006/11 ASAHI KASEI [AK4647] MIC Gain Amplifier The AK4647 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (see Table 18). The typical input impedance is 60k(typ)@MGAIN1-0 bits = "00" or 30k(typ)@MGAIN1-0 bits = "01", "10" or "11". MGAIN1 bit 0 0 1 1 MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 18. Mic Input Gain Default MIC Power When PMMP bit = "1", the MPWR pin supplies power for the microphone. This output voltage is typically 0.75 x AVDD and the load resistance is minimum 0.5k. In case of using two sets of stereo mic, the load resistance is minimum 2k for each channel. No capacitor must not be connected directly to MPWR pin (see Figure 23). PMMP bit MPWR pin 0 Hi-Z 1 Output Table 19. MIC Power MIC Power MPWR pin Default 2k 2k 2k 2k Microphone LIN1 pin Microphone RIN1 pin Microphone LIN2 pin Microphone RIN2 pin Figure 23. MIC Block Circuit MS0566-E-00 - 29 - 2006/11 ASAHI KASEI [AK4647] Digital EQ/HPF/LPF The AK4647 performs wind-noise reduction filter, stereo separation emphasis, gain compensation and ALC (Automatic Level Control) by digital domain for A/D converted data (Figure 24). FIL1, FIL3 and EQ blocks are IIR filters of 1st order. The filter coefficient of FIL3, EQ and FIL1 blocks can be set to any value. Refer to the section of "ALC operation" about ALC. When only DAC is powered-up, digital EQ/HPF/LPF circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, digital EQ/HPF/LPF circuit operates at recording path. Even if the path is switched from recording to playback, the register setting of filter coefficient at recording remains. Therefore, FIL3, EQ, FIL1 and GN1-0 bits should be set to "0" if digital EQ/HPF/LPF is not used for playback path. PMADL bit, PMADR bit LOOP bit Status Digital EQ/HPF/LPF x Power-down Power-down "00" x Playback Playback path x Recording Recording path "01", "10" or "11" 0 Recording & Playback Recording path 1 1 Recording Monitor Playback Recording path Note 32. Stereo separation emphasis circuit is effective only at stereo operation. Table 20. Digital EQ/HPF/LPF Cirtcuit Setting (x: Don't care) PMDAC bit 0 1 0 Default FIL3 coefficient also sets the attenuation of the stereo separation emphasis. The combination of GN1-0 bit (Table 21) and EQ coefficient set the compensation gain. FIL1 and FIL3 blocks become HPF when F1AS and F3AS bits are "0" and become LPF when F1AS and F3AS bits are "1", respectively. When EQ and FIL1 bits are "0", EQ and FIL1 blocks become "through" (0dB). When FIL3 bit is "0", FIL3 block become "MUTE". When each filter coefficient is changed, each filter should be set to "through" ("MUTE" in case of FIL3). Wind-noise reduction Stereo separation emphasis Gain compensation FIL1 An y coefficient F1A13-0 F1B13-0 F1AS FIL3 An y coefficient 0dB -10dB F3A13-0 MUTE F3B13-0 (set by F3AS FIL3 coefficient) EQ Gain ALC An y coefficient GN1-0 EQA15-0 +24/+12/0dB EQB13-0 EQC15-0 +12dB 0dB Figure 24. Digital EQ/HPF/LPF GN1 GN0 Gain 0 0 0dB Default 0 1 +12dB 1 x +24dB Table 21. Gain select of gain block (x: Don't care) MS0566-E-00 - 30 - 2006/11 ASAHI KASEI [AK4647] [Filter Coefficient Setting] 1) When FIL1 and FIL2 are set to "HPF" fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of should be set to 0dB.) Register setting FIL1: F1AS bit = "0", F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = "0", F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) 1 / tan (fc/fs) A = 10K/20 x 1 + 1 / tan (fc/fs) , B= 1 + 1 / tan (fc/fs) 1 - 1 / tan (fc/fs) Transfer function 1-z H(z) = A -1 Amplitude 2 - 2cos (2f/fs) M(f) = A 1 + B2 + 2Bcos (2f/fs) (f) = tan -1 Phase (B+1)sin (2f/fs) 1 - B + (B-1)cos (2f/fs) 1 + Bz -1 2) When FIL1 and FIL2 are set to "LPF" fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of FIL1 should be set to 0dB.) Register setting FIL1: F1AS bit = "1", F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = "1", F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) 1 A = 10K/20 x 1 + 1 / tan (fc/fs) , B= 1 + 1 / tan (fc/fs) 1 - 1 / tan (fc/fs) Transfer function 1+z H(z) = A -1 Amplitude 2 + 2cos (2f/fs) M(f) = A 1 + B2 + 2Bcos (2f/fs) (f) = tan -1 Phase (B-1)sin (2f/fs) 1 + B + (B+1)cos (2f/fs) 1 + Bz -1 MS0566-E-00 - 31 - 2006/11 ASAHI KASEI [AK4647] 3) EQ fs: Sampling frequency fc1: Pole frequency fc2: Zero-point frequency f: Input signal frequency K: Filter gain [dB] (Maximum +12dB) Register setting EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C (MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0) A = 10K/20 x 1 + 1 / tan (fc2/fs) , 1 + 1 / tan (fc1/fs) B= 1 + 1 / tan (fc1/fs) 1 - 1 / tan (fc1/fs) , C =10K/20 x 1 - 1 / tan (fc2/fs) 1 + 1 / tan (fc1/fs) Transfer function A + Cz H(z) = -1 Amplitude A + C + 2ACcos (2f/fs) M(f) = 1 + B2 + 2Bcos (2f/fs) 2 2 Phase (f) = tan -1 (AB-C)sin (2f/fs) A + BC + (AB+C)cos (2f/fs) 1 + Bz -1 [Translation the filter coefficient calculated by the equations above from real number to binary code (2's complement)] X = (Real number of filter coefficient calculated by the equations above) x 213 X should be rounded to integer, and then should be translated to binary code (2's complement). MSB of each filter coefficient setting register is sine bit. [Filter Coefficient Setting Example] 1) FIL1 block Example: HPF, fs=44.1kHz, fc=100Hz F1AS bit = "0" F1A[13:0] bits = 01 1111 1100 0110 F1B[13:0] bits = 10 0000 0111 0100 2) EQ block Example: fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB Gain[dB] +8dB fc1 fc2 Frequency EQA[15:0] bits = 0000 1001 0110 1110 EQB[13:0] bits = 10 0001 0101 1001 EQC[15:0] bits = 1111 1001 1110 1111 MS0566-E-00 - 32 - 2006/11 ASAHI KASEI [AK4647] ALC Operation The ALC (Automatic Level Control) is done by ALC block when ALC bit is "1". When only DAC is powered-up, ALC circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, ALC circuit operates at recording path. PMADL bit, PMADR bit "00" "01", "10" or "11" PMDAC bit 0 1 0 1 LOOP bit Status x Power-down x Playback x Recording 0 Recording & Playback 1 Recording Monitor Playback Table 22. ALC Setting (x: Don't care) ALC Power-down Playback path Recording path Recording path Recording path Default 1. ALC Limiter Operation During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 23), the IVL and IVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (Table 24). When ZELMN bit = "0" (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout period of both ALC limiter and recovery operation (Table 25). When ZELMN bit = "1" (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by ALC limiter operation. Attenuation step is fixed to 1 step regardless as the setting of LMAT1-0 bits. The attenuation operation is done continuously until the input signal level becomes ALC limiter detection level (Table 23) or less. After completing the attenuation operation, unless ALC bit is changed to "0", the operation repeats when the input signal level exceeds LMTH1-0 bits. LMTH1 0 0 1 1 LMTH0 ALC Limier Detection Level ALC Recovery Waiting Counter Reset Level 0 ALC Output -2.5dBFS -2.5dBFS > ALC Output -4.1dBFS 1 ALC Output -4.1dBFS -4.1dBFS > ALC Output -6.0dBFS 0 ALC Output -6.0dBFS -6.0dBFS > ALC Output -8.5dBFS 1 ALC Output -8.5dBFS -8.5dBFS > ALC Output -12dBFS Table 23. ALC Limiter Detection Level / Recovery Counter Reset Level ZELMN 0 1 LMAT1 LMAT0 ALC Limiter ATT Step 0 0 1 step 0.375dB 0 1 2 step 0.750dB 1 0 4 step 1.500dB 1 1 8 step 3.000dB x x 1step 0.375dB Table 24. ALC Limiter ATT Step (x: Don't care) Default Default ZTM1 0 0 1 1 ZTM0 0 1 0 1 Zero Crossing Timeout Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 25. ALC Zero Crossing Timeout Period Default MS0566-E-00 - 33 - 2006/11 ASAHI KASEI [AK4647] 2. ALC Recovery Operation The ALC recovery operation waits for the WTM1-0 bits (Table 26) to be set after completing the ALC limiter operation. If the input signal does not exceed "ALC recovery waiting counter reset level" (Table 23) during the wait time, the ALC recovery operation is done. The IVL and IVR values are automatically incremented by RGAIN1-0 bits (Table 27) up to the set reference level (Table 28) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 25). Then the IVL and IVR are set to the same value for both channels. The ALC recovery operation is done at a period set by WTM1-0 bits. When zero cross is detected at both channels during the wait period set by WTM1-0 bits, the ALC recovery operation waits until WTM1-0 period and the next recovery operation is done. For example, when the current IVOL value is 30H and RGAIN1-0 bits are set to "01", IVOL is changed to 32H by the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds the reference level (REF7-0), the IVOL values are not increased. When "ALC recovery waiting counter reset level (LMTH1-0) Output Signal < ALC limiter detection level (LMTH1-0)" during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When "ALC recovery waiting counter reset level (LMTH1-0) > Output Signal", the waiting timer of ALC recovery operation starts. The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation becomes faster than a normal recovery operation. When large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. WTM1 0 0 1 1 WTM0 0 1 0 1 ALC Recovery Operation Waiting Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 26. ALC Recovery Operation Waiting Period RGAIN0 GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 27. ALC Recovery GAIN Step Default RGAIN1 0 0 1 1 Default REF7-0 GAIN(dB) Step F1H +36.0 F0H +35.625 EFH +35.25 : : E2H +30.375 0.375dB E1H +30.0 Default E0H +29.625 : : 03H -53.25 02H -53.625 01H -54.0 00H MUTE Table 28. Reference Level at ALC Recovery operation MS0566-E-00 - 34 - 2006/11 ASAHI KASEI [AK4647] 3. Example of ALC Operation Table 29 shows the examples of the ALC setting for mic recording. Register Name LMTH1-0 ZELMN ZTM1-0 WTM1-0 REF7-0 IVL7-0, IVR7-0 LMAT1-0 RGAIN1-0 ALC Comment Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM1-0 bits should be the same or longer data as ZTM1-0 bits. Maximum gain at recovery operation Gain of IVOL Limiter ATT step Recovery GAIN step ALC enable fs=8kHz Operation -4.1dBFS Enable 32ms 32ms +30dB +30dB fs=44.1kHz Operation -4.1dBFS Enable 23.2ms 23.2ms +30dB +30dB 1 step 1 step Enable Data 01 0 01 01 E1H E1H Data 01 0 11 11 E1H E1H 00 00 1 00 1 step 00 1 step 1 Enable Table 29. Example of the ALC setting The following registers should not be changed during the ALC operation. These bits should be changed after the ALC operation is finished by ALC bit = "0" or PMADL=PMADR bits = "0". * LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN Example: Limiter = Zero crossing Enable Recovery Cycle = 32ms@8kHz Zero Crossing Timeout Period = 32ms@8kHz Limiter and Recovery Step = 1 Gain of IVOL = +30dB Maximum Gain = +30.0dB Limiter Detection Level = -4.1dBFS ALC bit = "1" Manual Mode WR (ZTM1-0, WTM2-0) (1) Addr=06H, Data=14H WR (REF7-0) (2) Addr=08H, Data=E1H WR (IVL/R7-0) * The value of IVOL should be the same or smaller than REF's (3) Addr=09H&0CH, Data=E1H WR (RGAIN1, LMTH1) (4) Addr=0BH, Data=00H WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= "1") (5) Addr=07H, Data=21H ALC Operation Note : WR : Write Figure 25. Registers set-up sequence at ALC operation MS0566-E-00 - 35 - 2006/11 ASAHI KASEI [AK4647] Input Digital Volume (Manual Mode) The input digital volume becomes a manual mode when ALC bit is "0". This mode is used in the case shown below. 1. 2. 3. After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH and etc) When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed. For example; when the change of the sampling frequency. When IVOL is used as a manual volume. IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 30). The IVOL value is changed at zero crossing or timeout. Zero crossing timeout period is set by ZTM1-0 bits. If IVL7-0 or IVR7-0 bits are written during PMADL=PMADR bits = "0", IVOL operation starts with the written values at the end of the ADC initialization cycle after PMADL or PMADR bit is changed to "1". Even if the path is switched from recording to playback, the register setting of IVOL remains. Therefore, IVL7-0 and IVR7-0 bits should be set to "91H" (0dB). IVL7-0 IVR7-0 F1H F0H EFH : E2H E1H E0H : 03H 02H 01H 00H GAIN (dB) Step +36.0 +35.625 +35.25 : +30.375 0.375dB +30.0 +29.625 : -53.25 -53.625 -54 MUTE Table 30. Input Digital Volume Setting Default MS0566-E-00 - 36 - 2006/11 ASAHI KASEI [AK4647] When writing to the IVL7-0 and IVR7-0 bits continuouslly, the control register should be written by an interval more than zero crossing timeout. If not, IVL and IVR are not changed since zero crossing counter is reset at every write operation. If the same register value as the previous write operation is written to IVL and IVR, this write operation is ignored and zero crossing counter is not reset. Therefore, IVL and IVR can be written by an interval less than zero crossing timeout. ALC bit ALC Status Disable Enable Disable IVL7-0 bits E1H(+30dB) IVR7-0 bits C6H(+20dB) Internal IVL E1H(+30dB) (1) E1(+30dB) --> F1(+36dB) E1(+30dB) (2) Internal IVR C6H(+20dB) E1(+30dB) --> F1(+36dB) C6H(+20dB) Figure 26. IVOL value during ALC operation (1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts. The wait time from ALC bit = "1" to ALC operation start by IVL7-0 bits is at most recovery time (WTM1-0 bits) plus zerocross timeout period (ZTM1-0 bits). (2) Writing to IVL and IVR registers (09H and 0CH) is ignored during ALC operation. After ALC is disabled, the IVOL changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to "1" by an interval more than zero crossing timeout period after ALC bit = "0". MS0566-E-00 - 37 - 2006/11 ASAHI KASEI [AK4647] De-emphasis Filter The AK4647 includes the digital de-emphasis filter (tc = 50/15s) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 31). DEM1 0 0 1 1 DEM0 Mode 0 44.1kHz 1 OFF Default 0 48kHz 1 32kHz Table 31. De-emphasis Control Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 32). If the BST1-0 bits are set to "01" (MIN Level), use a 47F capacitor for AC-coupling. If the boosted signal exceeds full scale, the analog output clips to the full scale. Figure 27 shows the boost frequency response at -20dB signal input. Boost Filter (fs=44.1kHz) 0 MAX -5 Gain [dB] MID -10 MIN -15 -20 -25 10 100 Frequency [Hz] Figure 27. Bass Boost Frequency Response (fs=44.1kHz) BST1 0 0 1 1 BST0 Mode 0 OFF 1 MIN 0 MID 1 MAX Table 32. Bass Boost Control 1000 10000 Default MS0566-E-00 - 38 - 2006/11 ASAHI KASEI [AK4647] Digital Output Volume The AK4647 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and DVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to -115dB or MUTE. When the DVOLC bit = "1", the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit = "0", the DVL7-0 bits control Lch level and DVR7-0 bits control Rch level. This volume has a soft transition function. The DVTM bit sets the transition time between set values of DVL/R7-0 bits as either 1061/fs or 256/fs (Table 34). When DVTM bit = "0", a soft transition between the set values occurs (1062 levels). It takes 1061/fs (=24ms@fs=44.1kHz) from 00H (+12dB) to FFH (MUTE). DVL/R7-0 00H 01H 02H : 18H : FDH FEH FFH Gain Step +12.0dB +11.5dB +11.0dB : 0.5dB 0dB : -114.5dB -115.0dB MUTE (-) Table 33. Digital Volume Code Table Default DVTM bit 0 1 Transition time between DVL/R7-0 bits = 00H and FFH Setting fs=8kHz fs=44.1kHz 1061/fs 133ms 24ms 256/fs 32ms 6ms Table 34. Transition Time Setting of Digital Output Volume Default MS0566-E-00 - 39 - 2006/11 ASAHI KASEI [AK4647] Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit goes to "1", the output signal is attenuated by - ("0") during the cycle set by the DVTM bit. When the SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to the value set by the DVL/R7-0 bits during the cycle set of the DVTM bit. If the soft mute is cancelled within the cycle set by the DVTM bit after starting the operation, the attenuation is discontinued and returned to the value set by the DVL/R7-0 bits. The soft mute is effective for changing the signal source without stopping the signal transmission (Figure 28). SM U T E bit D VTM bit D V L/R 7-0 bits D V TM bit (1) (3) Attenuation - GD (2) Analog O utput GD Figure 28. Soft Mute Function (1) The output signal is attenuated until - ("0") by the cycle set by the DVTM bit. (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the value set by the DVL/R7-0 bits. MS0566-E-00 - 40 - 2006/11 ASAHI KASEI [AK4647] Analog Mixing : Mono Input When the PMBP bit is set to "1", the mono input is powered-up. When the BEEPH bit is set to "1", the input signal from the MIN pin is output to Headphone-Amp. When the BEEPL bit is set to "1", the input signal from the MIN pin is output to the stereo line output amplifier. The external resister Ri adjusts the signal level of MIN input. Table 35 and Table 36 show the typical gain example at Ri = 20k. This gain is in inverse proportion to Ri . Ri MIN BEEPL LOUT/ROUT pin BEEPH HPL/HPR pin Figure 29. Block Diagram of MIN pin LOVL bit 0 1 Table 35. MIN Input HPG bit 0 1 Table 36. MIN Input LOUT/ROUT 0dB Default +2dB LOUT/ROUT Output Gain (typ) at Ri = 20k HPL/HPR Default -20dB -16.4dB Headphone-Amp Output Gain (typ) at Ri = 20k MIN MIN MS0566-E-00 - 41 - 2006/11 ASAHI KASEI [AK4647] Stereo Line Output (LOUT/ROUT pins) When DACL bit is "1", Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When DACL bit is "0", output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10k (min.). When the PMLO bit = LOPS bit = "0", the stereo line output enters power-down mode and the output is pulled-down to AVSS by 100k(typ). When the LOPS bit is "1", stereo line output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit at LOPS bit = "1". In this case, output signal line should be pulled-down to AVSS by 20k after AC coupled as Figure 31. Rise/Fall time is 300ms(max) at C=1F. When PMLO bit = "1", LOPS bit = "0", stereo line output is in normal operation. LOVL bit set the gain of stereo line output. "DACL" "LOVL" LOUT pin DAC ROUT pin Figure 30. Stereo Line Output LOPS 0 1 PMLO Mode LOUT/ROUT pin 0 Power-down Pull-down to AVSS 1 Normal Operation Normal Operation 0 Power-save Fall down to AVSS 1 Power-save Rise up to VCOM Table 37. Stereo Line Output Mode Select (x: Don't care) LOVL Gain Output Voltage (typ) 0 0dB 0.6 x AVDD Default 1 +2dB 0.757 x AVDD Table 38. Stereo Line Output Volume Setting Default LOUT ROUT 1F 220 20k Figure 31. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit) MS0566-E-00 - 42 - 2006/11 ASAHI KASEI [AK4647] [Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)] (2 ) P M L O b it (1 ) L O P S b it (3 ) (4 ) (6 ) (5 ) L O U T , R O U T p in s 300 m s N o r m a l O u tp u t 300 m s Figure 32. Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit) (1) Set LOPS bit = "1". Stereo line output enters the power-save mode. (2) Set PMLO bit = "1". Stereo line output exits the power-down mode. LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1F and AVDD=3.3V. (3) Set LOPS bit = "0" after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode. Stereo line output is enabled. (4) Set LOPS bit = "1". Stereo line output enters power-save mode. (5) Set PMLO bit = "0". Stereo line output enters power-down mode. LOUT and ROUT pins fall down to AVSS. Fall time is 200ms (max 300ms) at C=1F and AVDD=3.3V. (6) Set LOPS bit = "0" after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode. MS0566-E-00 - 43 - 2006/11 ASAHI KASEI [AK4647] Headphone Output Power supply voltage for the Headphone-Amp is supplied from the HVDD pin and centered on the HVDD/2 voltage. The load resistance and output voltage are specified by HVDD voltage. HPG bit selects the output voltage (see Table 39). HVDD 2.6 5.25V 4.0 5.25V HPG bit 0 1 Output Voltage [Vpp] 0.6 x AVDD 0.91 x AVDD Load Resistance (min) 22 100 Table 39. Headphone-Amp Output Voltage and Load Resistance When the HPMTN bit is "0", the common voltage of Headphone-Amp falls and the outputs (HPL and HPR pins) go to "L" (HVSS). When the HPMTN bit is "1", the common voltage rises to HVDD/2. A capacitor between the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to HVDD voltage and the capacitor at MUTET pin. [Example]: A capacitor between the MUTET pin and ground = 1.0F, HVDD=3.3V: Rise/fall time constant: = 100ms(typ), 250ms(max) Time until the common goes to HVSS when HPMTN bit = "1" "0": 500ms(max) When PMHPL and PMHPR bits are "0", the Headphone-Amp is powered-down, and the outputs (HPL and HPR pins) go to "L" (HVSS). PMHPL bit, PMHPR bit HPMTN bit HPL pin, HPR pin (1) (2) (3) (4) Figure 33. Power-up/Power-down Timing for Headphone-Amp (1) Headphone-Amp power-up (PMHPL, PMHPR bit = "1"). The outputs are still HVSS. (2) Headphone-Amp common voltage rises up (HPMTN bit = "1"). Common voltage of Headphone-Amp is rising. (3) Headphone-Amp common voltage falls down (HPMTN bit = "0"). Common voltage of Headphone-Amp is falling. (4) Headphone-Amp power-down (PMHPL, PMHPR bit = "0"). The outputs are HVSS. If the power supply is switched off or Headphone-Amp is powered-down before the common voltage goes to HVSS, some POP noise occurs. MS0566-E-00 - 44 - 2006/11 ASAHI KASEI [AK4647] When BOOST=OFF, the cut-off frequency (fc) of Headphone-Amp depends on the external resistor and capacitor. This fc can be shifted to lower frequency by using bass boost function. Table 40 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16. Output powers are shown at HVDD = 3.0, 3.3 and 5.0V. The output voltage of headphone is 0.6 x AVDD (Vpp) @HPG bit = "0" and 0.91 x AVDD (Vpp) @HPG bit = "1". When an external resistor R is smaller than 12, put an oscillation prevention circuit (0.22F20% capacitor and 1020% resistor) because it has the possibility that Headphone-Amp oscillates. HP-AMP R C Headphone 16 AK4647 0.22 10 Figure 34. External Circuit Example of Headphone HPG bit R [] 6.8 C [F] 100 47 100 47 220 100 22 10 fc [Hz] BOOST=OFF 0 16 0 1 100 fc [Hz] BOOST=MIN @fs=44.1kHz 70 28 149 78 50 19 106 47 45 17 100 43 62 25 137 69 Table 40. External Circuit Example Output Power [mW]@0dBFS 2.7V 10.1 5.1 33 0.9 3.0V 12.5 6.3 41 1.1 3.3V 15.1 7.7 50 1.3 MS0566-E-00 - 45 - 2006/11 ASAHI KASEI [AK4647] Serial Control Interface (1) 3-wire Serial Control Mode (I2C pin = "L") Internal registers may be written by using the 3-wire P interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 2-bit Chip address (Fixed to "10"), Read/Write (Fixed to "1"), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge ("") of CCLK. Address and data are latched on the 16th CCLK rising edge ("") after CSN falling edge(""). Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by PDN pin = "L". CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 "1" "0" "1" C1-C0: R/W: A4-A0: D7-D0: Chip Address (C1 = "1", C0 = "0"); Fixed to "10" READ/WRITE ("1": WRITE, "0": READ); Fixed to "1" Register Address Control data Figure 35. Serial Control I/F Timing MS0566-E-00 - 46 - 2006/11 ASAHI KASEI [AK4647] (2) I2C-bus Control Mode (I2C pin = "H") The AK4647 supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at SDA and SCL pins should be connected to (DVDD+0.3)V or less voltage. (2)-1. WRITE Operations Figure 36 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 42). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit (R/W). The most significant six bits of the slave address are fixed as "001001". The next bit is CAD0 (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits (Figure 37). If the slave address matches that of the AK4647, the AK4647 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 43). A R/W bit value of "1" indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4647. The format is MSB first, and those most significant 2-bits are fixed to zeros (Figure 38). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 39). The AK4647 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 42). The AK4647 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4647 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 24H prior to generating a stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 44) except for the START and STOP conditions. S T A R T R/W="0" S T O P Sub Address(n) Data(n) A C K A C K Data(n+1) A C K A C K Data(n+x) A C K P SDA Slave S Address A C K Figure 36. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 1 CAD0 R/W (Those CAD0 should match with CAD0 pins) Figure 37. The First Byte 0 0 0 A4 A3 A2 A1 A0 Figure 38. The Second Byte D7 D6 D5 D4 D3 D2 D1 D0 Figure 39. Byte Structure after the second byte MS0566-E-00 - 47 - 2006/11 ASAHI KASEI [AK4647] (2)-2. READ Operations Set the R/W bit = "1" for the READ operation of the AK4647. After transmission of data, the master can read the next address's data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 24H prior to generating a stop condition, the address counter will "roll over" to 00H and the data of 00H will be read out. The AK4647 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. (2)-2-1. CURRENT ADDRESS READ The AK4647 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to "1", the AK4647 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4647 ceases transmission. S T A R T R/W="1" S T O P Data(n) Data(n+1) A C K A C K Data(n+2) A C K A C K Data(n+x) A C K P SDA Slave S Address A C K Figure 40. CURRENT ADDRESS READ (2)-2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start request, a slave address (R/W bit = "0") and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit set to "1". The AK4647 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4647 ceases transmission. S T A R T S T A R T Sub Address(n) A C K A C K R/W="0" R/W="1" S T O P Data(n) Data(n+1) A C K A C K A C K Data(n+x) A C K P SDA Slave S Address Slave S Address A C K Figure 41. RANDOM ADDRESS READ MS0566-E-00 - 48 - 2006/11 ASAHI KASEI [AK4647] SDA SCL S start condition P stop condition Figure 42. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S clock pulse for acknowledgement 1 2 8 9 START CONDITION Figure 43. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 44. Bit Transfer on the I2C-Bus MS0566-E-00 - 49 - 2006/11 ASAHI KASEI [AK4647] Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Lch Input Volume Control Lch Digital Volume Control ALC Mode Control 3 Rch Input Volume Control Rch Digital Volume Control Mode Control 3 Mode Control 4 Power Management 3 Digital Filter Select FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 D7 0 0 0 LOVL PLL3 PS1 DVTM 0 REF7 D6 PMVCM HPMTN 0 LOPS PLL2 PS0 0 0 REF6 D5 PMBP PMHPL 0 MGAIN1 PLL1 FS3 ZTM1 ALC REF5 D4 0 PMHPR DACL 0 PLL0 0 ZTM0 ZELMN REF4 D3 PMLO M/S 0 0 BCKO 0 WTM1 LMAT1 REF3 D2 PMDAC 0 PMMP BEEPL 0 FS2 WTM0 LMAT0 REF2 D1 0 MCKO 0 0 DIF1 FS1 0 RGAIN0 REF1 D0 PMADL PMPLL MGAIN0 0 DIF0 FS0 0 LMTH0 REF0 IVL7 DVL7 RGAIN1 IVR7 DVR7 0 0 0 GN1 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 IVL6 DVL6 LMTH1 IVR6 DVR6 LOOP 0 0 GN0 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 IVL5 DVL5 0 IVR5 DVR5 SMUTE 0 HPG 0 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 IVL4 DVL4 0 IVR4 DVR4 DVOLC 0 MDIF2 FIL1 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 IVL3 DVL3 0 IVR3 DVR3 BST1 IVOLC MDIF1 EQ F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 IVL2 DVL2 0 IVR2 DVR2 BST0 HPM INR FIL3 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 IVL1 DVL1 0 IVR1 DVR1 DEM1 BEEPH INL 0 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 IVL0 DVL0 0 IVR0 DVR0 DEM0 DACH PMADR 0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 Note 33. PDN pin = "L" resets the registers to their default values. Note 34. Unused bits must contain a "0" value. MS0566-E-00 - 50 - 2006/11 ASAHI KASEI [AK4647] Register Definitions Addr 00H Register Name Power Management 1 Default D7 0 0 D6 PMVCM 0 D5 PMBP 0 D4 0 0 D3 PMLO 0 D2 PMDAC 0 D1 0 0 D0 PMADL 0 PMADL: MIC-Amp Lch and ADC Lch Power Management 0: Power-down (Default) 1: Power-up When the PMADL or PMADR bit is changed from "0" to "1", the initialization cycle (1059/fs=24ms @44.1kHz) starts. After initializing, digital data of the ADC is output. PMDAC: DAC Power Management 0: Power-down (Default) 1: Power-up PMLO: Stereo Line Out Power Management 0: Power-down (Default) 1: Power-up PMBP: Mono Input Power Management 0: Power-down (Default) 1: Power-up Both PMDAC and PMBP bits should be set to "1" when DAC is powered-up for playback. PMVCM: VCOM Power Management 0: Power-down (Default) 1: Power-up When any blocks are powered-up, the PMVCM bit must be set to "1". PMVCM bit can be set to "0" only when all power management bits of 00H, 01H, 02H, 10H, 20H and MCKO bits are "0". Each block can be powered-down respectively by writing "0" in each bit of this address. When the PDN pin is "L", all blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value. When all power management bits are "0" in the 00H, 01H, 02H, 10H and 20H addresses and MCKO bit is "0", all blocks are powered-down. The register values remain unchanged. Power supply current is 20A(typ) in this case. For fully shut down (typ. 1A), PDN pin should be "L". When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks must always be present. MS0566-E-00 - 51 - 2006/11 ASAHI KASEI [AK4647] Addr 01H Register Name Power Management 2 Default D7 0 0 D6 HPMTN 0 D5 PMHPL 0 D4 PMHPR 0 D3 M/S 0 D2 0 0 D1 MCKO 0 D0 PMPLL 0 PMPLL: PLL Power Management 0: EXT Mode and Power-Down (Default) 1: PLL Mode and Power-up MCKO: Master Clock Output Enable 0: Disable: MCKO pin = "L" (Default) 1: Enable: Output frequency is selected by PS1-0 bits. M/S: Master / Slave Mode Select 0: Slave Mode (Default) 1: Master Mode PMHPR: Headphone-Amp Rch Power Management 0: Power-down (Default) 1: Power-up PMHPL: Headphone-Amp Lch Power Management 0: Power-down (Default) 1: Power-up HPMTN: Headphone-Amp Mute Control 0: Mute (Default) 1: Normal operation Addr 02H Register Name Signal Select 1 Default D7 0 0 D6 0 0 D5 0 0 D4 DACL 0 D3 0 0 D2 PMMP 0 D1 0 0 D0 MGAIN0 1 MGAIN1-0: MIC-Amp Gain Control (See Table 18) MGAIN1 bit is D5 bit of 03H. PMMP: MPWR pin Power Management 0: Power-down: Hi-Z (Default) 1: Power-up DACL: Switch Control from DAC to Stereo Line Output 0: OFF (Default) 1: ON When PMLO bit is "1", DACL bit is enabled. When PMLO bit is "0", the LOUT/ROUT pins go to AVSS. MS0566-E-00 - 52 - 2006/11 ASAHI KASEI [AK4647] Addr 03H Register Name Signal Select 2 Default D7 LOVL 0 D6 LOPS 0 D5 MGAIN1 0 D4 0 0 D3 0 0 D2 BEEPL 0 D1 0 0 D0 0 0 BEEPL: Switch Control from MIN pin to Stereo Line Output 0: OFF (Default) 1: ON When PMLO bit is "1", BEEPL bit is enabled. When PMLO bit is "0", the LOUT/ROUT pins go to AVSS. MGAIN1: MIC-Amp Gain Control (See Table 18) LOPS: Stereo Line Output Power-Save Mode 0: Normal Operation (Default) 1: Power-Save Mode LOVL: Stereo Line Output Gain Select (Table 38) 0: 0dB (Default) 1: +2dB Addr 04H Register Name Mode Control 1 Default D7 PLL3 0 D6 PLL2 0 D5 PLL1 0 D4 PLL0 0 D3 BCKO 0 D2 0 0 D1 DIF1 1 D0 DIF0 0 DIF1-0: Audio Interface Format (See Table 13) Default: "10" (Left jutified) BCKO: BICK Output Frequency Select at Master Mode (See Table 10) PLL3-0: PLL Reference Clock Select (See Table 4) Default: "0000"(LRCK pin) Addr 05H Register Name Mode Control 2 Default D7 PS1 0 D6 PS0 0 D5 FS3 0 D4 0 0 D3 0 0 D2 FS2 0 D1 FS1 0 D0 FS0 0 FS3-0: Sampling Frequency Select (See Table 5 and Table 6.) and MCKI Frequency Select (See Table 11.) FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode. PS1-0: MCKO Output Frequency Select (Table 9) Default: "00"(256fs) MS0566-E-00 - 53 - 2006/11 ASAHI KASEI [AK4647] Addr 06H Register Name Timer Select Default D7 DVTM 0 D6 0 0 D5 ZTM1 0 D4 ZTM0 0 D3 WTM1 0 D2 WTM0 0 D1 0 0 D0 0 0 WTM1-0: ALC Recovery Waiting Period (see Table 26.) Default: "00" (128/fs) ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (see Table 25.) Default: "00" (128/fs) DVTM: Digital Volume Transition Time Setting (see Table 34.) 0: 1061/fs (Default) 1: 256/fs This is the transition time between DVL/R7-0 bits = 00H and FFH. Addr 07H Register Name ALC Mode Control 1 Default D7 0 0 D6 0 0 D5 ALC 0 D4 ZELMN 0 D3 LMAT1 0 D2 LMAT0 0 D1 RGAIN0 0 D0 LMTH0 0 LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (see Table 23.) Default: "00" LMTH1 bit is D6 bit of 0BH. RGAIN1-0: ALC Recovery GAIN Step (see Table 27.) Default: "00" RGAIN1 bit is D7 bit of 03H. LMAT1-0: ALC Limiter ATT Step (see Table 24.) Default: "00" ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation 0: Enable (Default) 1: Disable ALC: ALC Enable 0: ALC Disable (Default) 1: ALC Enable Addr 08H Register Name ALC Mode Control 2 Default D7 REF7 1 D6 REF6 1 D5 REF5 1 D4 REF4 0 D3 REF3 0 D2 REF2 0 D1 REF1 0 D0 REF0 1 REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (see Table 28.) Default: "E1H" (+30.0dB) MS0566-E-00 - 54 - 2006/11 ASAHI KASEI [AK4647] Addr 09H 0CH Register Name Lch Input Volume Control Rch Input Volume Control Default D7 IVL7 IVR7 1 D6 IVL6 IVR6 1 D5 IVL5 IVR5 1 D4 IVL4 IVR4 0 D3 IVL3 IVR3 0 D2 IVL2 IVR2 0 D1 IVL1 IVR1 0 D0 IVL0 IVR0 1 IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (see Table 30.) Default: "E1H" (+30.0dB) Addr 0AH 0DH Register Name Lch Digital Volume Control Rch Digital Volume Control Default D7 DVL7 DVR7 0 D6 DVL6 DVR6 0 D5 DVL5 DVR5 0 D4 DVL4 DVR4 1 D3 DVL3 DVR3 1 D2 DVL2 DVR2 0 D1 DVL1 DVR1 0 D0 DVL0 DVR0 0 DVL7-0, DVR7-0: Output Digital Volume (see Table 33.) Default: "18H" (0dB) Addr 0BH Register Name ALC Mode Control 3 Default D7 RGAIN1 0 D6 LMTH1 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 LMTH1: ALC Limiter Detection Level / Recovery Counter Reset Level (see Table 23.) RGAIN1: ALC Recovery GAIN Step (see Table 27.) Addr 0EH Register Name Mode Control 3 Default D7 0 0 D6 LOOP 0 D5 SMUTE 0 D4 DVOLC 1 D3 BST1 0 D2 BST0 0 D1 DEM1 0 D0 DEM0 1 DEM1-0: De-emphasis Frequency Select (Table 31) Default: "01" (OFF) BST1-0: Bass Boost Function Select (Table 32) Default: "00" (OFF) DVOLC: Output Digital Volume Control Mode Select 0: Independent 1: Dependent (Default) When DVOLC bit = "1", DVL7-0 bits control both Lch and Rch volume level, while register values of DVL7-0 bits are not written to DVR7-0 bits. When DVOLC bit = "0", DVL7-0 bits control Lch level and DVR7-0 bits control Rch level, respectively. SMUTE: Soft Mute Control 0: Normal Operation (Default) 1: DAC outputs soft-muted LOOP: Digital Loopback Mode 0: SDTI DAC (Default) 1: SDTO DAC MS0566-E-00 - 55 - 2006/11 ASAHI KASEI [AK4647] Addr 0FH Register Name Mode Control 4 Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 IVOLC 1 D2 HPM 0 D1 BEEPH 0 D0 DACH 0 DACH: Switch Control from DAC to Headphone-Amp 0: OFF (Default) 1: ON BEEPH: Switch Control from MIN pin to Headphone-Amp 0: OFF (Default) 1: ON HPM: Headphone-Amp Mono Output Select 0: Stereo (Default) 1: Mono When the HPM bit = "1", DAC output signal is output to Lch and Rch of the Headphone-Amp as (L+R)/2 IVOLC: Input Digital Volume Control Mode Select 0: Independent 1: Dependent (Default) When IVOLC bit = "1", IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0 bits are not written to IVR7-0 bits. When IVOLC bit = "0", IVL7-0 bits control Lch level and IVR7-0 bits control Rch level, respectively. Addr 10H Register Name Power Management 3 Default D7 0 0 D6 0 0 D5 HPG 0 D4 MDIF2 0 D3 MDIF1 0 D2 INR 0 D1 INL 0 D0 PMADR 0 PMADR: MIC-Amp Lch and ADC Rch Power Management 0: Power-down (Default) 1: Power-up INL: ADC Lch Input Source Select 0: LIN1 pin (Default) 1: LIN2 pin INR: ADC Rch Input Source Select 0: RIN1 pin (Default) 1: RIN2 pin MDIF1: Single-ended / Full-differential Input Select 1 0: Single-ended input (LIN1/RIN1 pins: Default) 1: Full-differential input (IN1+/IN1- pins) MDIF1 bit selects the input type of pins #46 and #47. MDIF2: Single-ended / Full-differential Input Select 2 0: Single-ended input (LIN2/RIN2 pins: Default) 1: Full-differential input (IN2+/IN2- pins) MDIF2 bit selects the input type of pins #45 and #44. HPG: Headphone-Amp Gain Select (see Table 39) 0: 0dB (Default) 1: +3.6dB MS0566-E-00 - 56 - 2006/11 ASAHI KASEI [AK4647] Addr 11H Register Name Digital Filter Select Default D7 GN1 0 D6 GN0 0 D5 0 0 D4 FIL1 0 D3 EQ 0 D2 FIL3 0 D1 0 0 D0 0 0 GN1-0: Gain Select at GAIN block (See Table 21) Default: "00" FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable 0: Disable (Default) 1: Enable When FIL3 bit is "1", the settings of F3A13-0 and F3B13-0 bits are enabled. When FIL3 bit is "0", FIL3 block is OFF (MUTE). EQ: EQ (Gain Compensation Filter) Coefficient Setting Enable 0: Disable (Default) 1: Enable When EQ bit is "1", the settings of EQA15-0, EQB13-0 and EQC15-0 bits are enabled. When EQ bit is "0", EQ block is through (0dB). FIL1: FIL1 (Wind-noise Reduction Filter) Coefficient Setting Enable 0: Disable (Default) 1: Enable When FIL1 bit is "1", the settings of F1A13-0 and F1B13-0 bits are enabled. When FIL1 bit is "0", FIL1 block is through (0dB). MS0566-E-00 - 57 - 2006/11 ASAHI KASEI [AK4647] Addr 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register Name FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Default D7 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 0 D6 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 0 D5 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 0 D4 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 0 D3 F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 0 D2 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 0 D1 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 0 D0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 0 F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2) Default: "0000H" F3AS: FIL3 (Stereo Separation Emphasis Filter) Select 0: HPF (Default) 1: LPF EQA15-0, EQB13-0, EQC15-C0: EQ (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1) Default: "0000H" F1A13-0, F1B13-B0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2) Default: "0000H" F1AS: FIL1 (Wind-noise Reduction Filter) Select 0: HPF (Default) 1: LPF MS0566-E-00 - 58 - 2006/11 ASAHI KASEI [AK4647] SYSTEM DESIGN Figure 45 and shows the system connection diagram for the AK4647. An evaluation board [AKD4647] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Headphone 47u 47u Power Supply 2.6 3.6V 10u 6.8 10 1u 0.22u MUTET 36 HPL 35 HPR 34 0.1u 10 0.22u 6.8 HVSS 33 HVDD 32 TEST2 31 TEST1 30 NC 29 NC 28 MCKO 27 MCKI 26 20k 20k 37 NC NC 25 NC 24 DVSS 23 DVDD 22 BICK 21 200 Line Out 200 38 NC 0.1u 1u 1u 39 ROUT 40 LOUT 41 NC Mono In 42 MIN 43 NC AK4647VQ Top View LRCK 20 NC 19 SDTO 18 SDTI 17 CDTI/SDA 16 CCLK/SCL 15 CSN/CAD0 14 NC 13 10 DSP External MIC 44 RIN2/IN2- 45 LIN2/IN2+ 46 LIN1/IN1- Internal MIC 47 RIN1/IN1+ 48 MPWR 2 VCOM 6 VCOC 5 AVDD 3 AVSS 9 PDN 7 I2C 8 NC P 11 NC 1 NC 4 NC 10 NC 2.2k 2.2k 2.2k 2.2k 0.1u 0.1u 2.2u Cp Analog Ground Digital Ground Notes: - AVSS, DVSS and HVSS of the AK4647 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When the AK4647 is EXT mode (PMPLL bit = "0"), a resistor and capacitor of VCOC pin is not needed. - When the AK4647 is PLL mode (PMPLL bit = "1"), a resistor and capacitor of VCOC pin is shown in Table 4. - When the AK4647 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to "1". Therefore, 100k around pull-up resistor should be connected to LRCK and BICK pins of the AK4647. Figure 45. Typical Connection Diagram (MIC Input) MS0566-E-00 - 59 - Rp 12 NC 2006/11 ASAHI KASEI [AK4647] Headphone 47u 47u Power Supply 2.6 3.6V 10u 6.8 10 10 1u 0.22u 0.22u 0.1u MUTET 36 HPL 35 6.8 HPR 34 HVSS 33 HVDD 32 TEST2 31 TEST1 30 NC 29 NC 28 MCKO 27 MCKI 26 20k 20k 37 NC NC 25 NC 24 DVSS 23 DVDD 22 BICK 21 200 Line Out 200 Mono In 38 NC 0.1u 1u 1u 39 ROUT 40 LOUT 41 NC 42 MIN 43 NC 44 RIN2/IN2- AK4647VQ Top View LRCK 20 NC 19 SDTO 18 SDTI 17 CDTI/SDA 16 CCLK/SCL 15 CSN/CAD0 14 NC 13 10 DSP Line In 45 LIN2/IN2+ 46 LIN1/IN1- 47 RIN1/IN1+ 48 MPWR 2 VCOM 6 VCOC 5 AVDD 3 AVSS 9 PDN 7 I2C 8 NC P 11 NC 1 NC 4 NC 10 NC 0.1u 0.1u 2.2u Cp Analog Ground Digital Ground Notes: - AVSS, DVSS and HVSS of the AK4647 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When the AK4647 is EXT mode (PMPLL bit = "0"), a resistor and capacitor of VCOC pin is not needed. - When the AK4647 is PLL mode (PMPLL bit = "1"), a resistor and capacitor of VCOC pin is shown in Table 4. - When the AK4647 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to "1". Therefore, 100k around pull-up resistor should be connected to LRCK and BICK pins of the AK4647. Figure 46. Typical Connection Diagram (Line Input) MS0566-E-00 - 60 - Rp 12 NC 2006/11 ASAHI KASEI [AK4647] 1. Grounding and Power Supply Decoupling The AK4647 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and HVDD are usually supplied from the system's analog supply. If AVDD, DVDD and HVDD are supplied separately, the power-up sequence is not critical. AVSS, DVSS and HVSS of the AK4647 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4647 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2F electrolytic capacitor in parallel with a 0.1F ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4647. 3. Analog Inputs The Mic, Line and MIN inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp(typ) @MGAIN1-0 bits = "01", 0.03 x AVDD Vpp(typ) @MGAIN1-0 bits = "10", 0.015 x AVDD Vpp(typ) @MGAIN1-0 bits = "11" or 0.6 x AVDD Vpp(typ) @MGAIN1-0 bits = "00" for the Mic/Line input and 0.6 x AVDD Vpp (typ) for the MIN input, centered around the internal common voltage (0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2RC). The AK4647 can accept input voltages from AVSS to AVDD. 4. Analog Outputs The input data format for the DAC is 2's complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). Stereo Line Output is centered at 0.45 x AVDD. The Headphone-Amp output is centered at HVDD/2. MS0566-E-00 - 61 - 2006/11 ASAHI KASEI [AK4647] CONTROL SEQUENCE Clock Set up When ADC or DAC is powered-up, the clocks must be supplied. 1. PLL Master Mode. Example: Power Supply (1) PDN pin (2) (3) Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz PMVCM bit (Addr:00H, D6) (4) MCKO bit (Addr:01H, D1) (1) Power Supply & PDN pin = "L" "H" PMPLL bit (Addr:01H, D0) (5) MCKI pin Input (2)Addr:01H, Data:08H Addr:04H, Data:4AH Addr:05H, Data:27H M/S bit (Addr:01H, D3) 40msec(max) (6) (3)Addr:00H, Data:40H Output 40msec(max) (8) BICK pin LRCK pin (4)Addr:01H, Data:0BH MCKO pin (7) Output MCKO, BICK and LRCK output Figure 47. Clock Set Up Sequence (1) MS0566-E-00 - 62 - 2006/11 ASAHI KASEI [AK4647] 2. PLL Slave Mode (LRCK or BICK pin) Example: Power Supply (1) PDN pin (2) (3) Audio I/F Format : MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 44.1kHz PMVCM bit (Addr:00H, D6) 4fs ofPower Supply & PDN pin = "L" (1) "H" PMPLL bit (Addr:01H, D0) (2) Addr:04H, Data:32H Addr:05H, Data:27H Input (4) LRCK pin BICK pin Internal Clock (3) Addr:00H, Data:40H (5) (4) Addr:01H, Data:01H Figure 48. Clock Set Up Sequence (2) MS0566-E-00 - 63 - 2006/11 ASAHI KASEI [AK4647] 3. PLL Slave Mode (MCKI pin) Example: Audio I/F Format: MSB justified (ADC & DAC) Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz Power Supply (1) (1) Power Supply & PDN pin = "L" (2) (3) "H" PDN pin PMVCM bit (Addr:00H, D6) (4) (2)Addr:04H, Data:4AH Addr:05H, Data:27H MCKO bit (Addr:01H, D1) (3)Addr:00H, Data:40H PMPLL bit (Addr:01H, D0) (5) MCKI pin Input 40msec(max) (6) (4)Addr:01H, Data:03H MCKO output start Output MCKO pin (7) (8) BICK pin LRCK pin Input BICK and LRCK input start Figure 49. Clock Set Up Sequence (3) MS0566-E-00 - 64 - 2006/11 ASAHI KASEI [AK4647] 4. EXT Slave Mode Example: Audio I/F Format: MSB justified (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz MCKO: Disable Power Supply (1) (1) Power Supply & PDN pin = "L" "H" PDN pin (2) (3) PMVCM bit (Addr:00H, D6) (4) (2) Addr:04H, Data:02H Addr:05H, Data:00H Input (4) MCKI pin LRCK pin BICK pin (3) Addr:00H, Data:40H Input MCKI, BICK and LRCK input Figure 50. Clock Set Up Sequence (4) MS0566-E-00 - 65 - 2006/11 ASAHI KASEI [AK4647] MIC Input Recording (Stereo) Example: PLL Master Mode Audio I/F Format:MSB justified (ADC & DAC) Sampling Frequency:44.1kHz Pre MIC AMP:+20dB MIC Power On ALC setting:Refer to Table 29 ALC bit="1" FS3-0 bits (Addr:05H, D5&D2-0) 0,000 (1) 1,111 (1) Addr:05H, Data:27H MIC Control (Addr:02H, D2-0) 001 (2) 101 3CH (3) (2) Addr:02H, Data:05H ALC Control 1 (Addr:06H) 00H E1H (4) (3) Addr:06H, Data:3CH ALC Control 2 (Addr:08H) E1H (4) Addr:08H, Data:E1H (5) Addr:0BH, Data:00H ALC Control 3 (Addr:0BH) 00H (5) 00H (6) Addr:07H, Data:21H ALC Control 4 (Addr:07H) 07H (6) 21H (9) 01H ALC Disable (7) Addr:00H, Data:41H Addr:10H, Data:01H ALC State PMADL/R bits (Addr:00H&10H, D0) ALC Disable ALC Enable Recording (8) Addr:00H, Data:40H Addr:10H, Data:00H 1059 / fs (7) (8) ADC Internal State Power Down Initialize Normal State Power Down (9) Addr:07H, Data:01H Figure 51. MIC Input Recording Sequence MS0566-E-00 - 66 - 2006/11 ASAHI KASEI [AK4647] Headphone-amp Output Example: FS3-0 bits (Addr:05H, D5&D2-0) 0,000 (1) (2) 1,111 (13) PLL, Master Mode Audio I/F Format :MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: -8dB Bass Boost level : Middle DACH bit (Addr:0FH, D0) (1) Addr:05H, Data:27H (2) Addr:0FH, Data:09H (3) Addr:0EH, Data:19H (4) Addr:09H&0CH, Data:91H (5) Addr:0AH&0DH, Data:28H BST1-0 bits (Addr:0EH, D3-2) 00 (3) 10 (12) 00 91H IVL/R7-0 bits (Addr:09H&0CH, D7-0) E1H (4) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) 18H (5) 28H (6) Addr:00H, Data:64H (7) Addr:01H, Data:39H PMDAC bit (Addr:00H, D2) (6) (11) (8) Addr:01H, Data:79H PMBP bit (Addr:00H, D5) Playback PMHPL/R bits (Addr:01H, D5-4) (7) (10) (9) Addr:01H, Data:39H (10) Addr:01H, Data:09H HPMTN bit (Addr:01H, D6) (8) (9) (11) Addr:00H, Data:40H HPL/R pins Normal Output (12) Addr:0EH, Data:11H (13) Addr:0FH, Data:08H Figure 52. Headphone-Amp Output Sequence MS0566-E-00 - 67 - 2006/11 ASAHI KASEI [AK4647] Stereo Line Output Example: PLL, Master Mode Audio I/F Format :MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: -8dB LOVL=MINL bits = "0" FS3-0 bits (Addr:05H, D5&D2-0) 0,000 (1) 1,111 (10) (1) Addr:05H, Data:27H (2) Addr:02H, Data:10H DACL bit (Addr:02H, D4) (2) IVL/R7-0 bits (Addr:09H&0CH, D7-0) E1H (3) 91H (3) Addr:09H&0CH, Data:91H (4) Addr:0AH&0DH, Data:28H DVL/R7-0 bits (Addr:0AH&0DH, D7-0) 18H (4) 28H (5) Addr:03H, Data:40H (6) Addr:00H, Data:6CH LOPS bit (Addr:03H, D6) (5) (7) (8) (11) PMDAC bit (Addr:00H, D2) (7) Addr:03H, Data:00H Playback (8) Addr:03H, Data:40H PMBP bit (Addr:00H, D5) (6) (9) PMLO bit (Addr:00H, D3) >300 ms (9) Addr:00H, Data:40H (10) Addr:02H, Data:00H >300 ms LOUT pin ROUT pin Normal Output (11) Addr:03H, Data:00H Figure 53. Stereo Lineout Sequence MS0566-E-00 - 68 - 2006/11 ASAHI KASEI [AK4647] Stop of Clock Master clock can be stopped when ADC and DAC are not used. 1. PLL Master Mode Example: (1) PMPLL bit (Addr:01H, D0) (2) Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO bit (Addr:01H, D1) "1" or "0" (3) (1) (2) Addr:01H, Data:08H (3) Stop an external MCKI External MCKI Input Figure 54. Clock Stopping Sequence (1) 2. PLL Slave Mode (LRCK or BICK pin) Example (1) PMPLL bit (Addr:01H, D0) (2) Audio I/F Format : MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs External BICK External LRCK Input (2) (1) Addr:01H, Data:00H Input (2) Stop the external clocks Figure 55. Clock Stopping Sequence (2) MS0566-E-00 - 69 - 2006/11 ASAHI KASEI [AK4647] 3. PLL Slave (MCKI pin) (1) Example Audio I/F Format: MSB justified (ADC & DAC) PLL Reference clock: MCKI BICK frequency: 64fs PMPLL bit (Addr:01H, D0) (1) MCKO bit (Addr:01H, D1) (2) (1) Addr:01H, Data:00H External MCKI Input (2) Stop the external clocks Figure 56. Clock Stopping Sequence (3) 4. EXT Slave Mode (1) External MCKI External BICK External LRCK Input Example (1) Input (1) Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs Input (1) Stop the external clocks Figure 57. Clock Stopping Sequence (4) Power down Power supply current can be shut down (typ. 10A) by stopping clocks and setting PMVCM bit = "0" after all blocks except for VCOM are powered-down. Power supply current can be also shut down (typ. 10A) by stopping clocks and setting PDN pin = "L". When PDN pin = "L", the registers are initialized. MS0566-E-00 - 70 - 2006/11 ASAHI KASEI [AK4647] PACKAGE 48pin LQFP(Unit:mm) 9.0 0.2 7.0 36 37 25 1.70Max 0.13 0.13 1.40 0.05 24 9.0 0.2 48 1 0.22 0.08 12 13 7.0 0.16 0.07 0.5 0.10 M 0 10 0.10 0.5 0.2 Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0566-E-00 - 71 - 2006/11 ASAHI KASEI [AK4647] MARKING AK4647VQ XXXXXXX 1 XXXXX : Date code identifier (5 digits) Revision History Date (YY/MM/DD) 06/11/10 Revision 00 Reason First Edition Page Contents MPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0566-E-00 - 72 - 2006/11 |
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